Referring to FIG. 1, a conventional memory device includes a memory cell array 10, a plurality of parallel bit lines 11 coupled to the memory cell array 10, and a plurality of parallel word lines 12 coupled to the memory cell array 10.
The memory cell array 10 includes a plurality of memory cells 13. The word lines 12 intersect the bit lines 11, and are electrically isolated from the bit lines 11. The word lines 12 transmit a control input to the memory cells 13 in order to control the memory cells 13 to output data stored therein to the bit lines 11.
As the demand for storage capacity of memory devices increases, memory cell arrays 10 with many more memory cells 13 would be preferable. However, to accommodate this, each bit line 11 is made longer to be coupled to more memory cells 13, which inevitably increases a capacitance seen thereat.
Because of the relatively large capacitance seen at each bit line 11, voltages outputted by the memory cells 13 may not promptly propagate to the bit lines 11 (i.e., the memory cells 13 may not be able to drive the bit lines 11 efficiently). As a result, a plurality of sense amplifiers 14 are employed to be coupled respectively to the bit lines 11 to assist in amplifying voltages on the bit lines 11 in order to facilitate data transmission and allow the memory device to operate at a higher frequency.
Nonetheless, the sense amplifiers 14 may be undesirable components of the memory device due to their relatively large power consumption. Therefore, it may be beneficial to attempt to address the issue of the capacitance seen at each bit line 11, and to omit the sense amplifiers 14 altogether.